The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, as the optical lithography approaches its technological and economical limits, multiple patterning processes are used for manufacturing patterns with small critical dimensions (CD) and/or small pitches. In a multiple patterning process, an IC layout is decomposed into two or more sub-layouts. A mask is made for each of the sub-layouts. Then the two or more masks are used to collectively manufacture (or pattern) a wafer using photolithography by overlapping an image of one mask with those of other masks onto the same layer of the wafer. Examples of such sub-layouts include main/cut layouts, mandrel/spacer/cut layouts, etc. In a multiple patterning process, merely optimizing a mask for a single patterning process is insufficient. A set of masks need to be collectively optimized to achieve a balanced performance between the individual patterning fidelity and the overlay budget among the masks.